Tags: Intel penryn six core specs release dateSun leaked "Dunnington" details.
Previous rumors have revealed true; Intel is indeed targeting a six-core processor at servers, it's 45nm based and shares "penryn" improvements like SSE4.
Details were leaked by Sun, in the form of parts of a presentation from Intel.
The L3 cache is confirmed to be of 16MB and the L2 cache is of 3MB shared by each pair of cores. This points to three "Wolfdale" cores with 3MB of L2 stuck together on the same die, instead of the same package. The four cores of the "Yorkfield" CPU are built with two dual core dies on the same package.
This is a significant step forward for Intel since it represents what is commonly called a native multi-core design. Intel took the decision to not move to a native quad-core design with "penryn" but "Dunnington" is a step in the same direction that "Nehalem" will take. The shared L2 cache, by each pair of cores, is still remnant of a design not thought for this kind of application and will go away for "Nehalem" cores.
To date AMD is the only one on the x86 market with a native quad-core design.
Previous specifications that pointed to pin compatibility with Tigerton have also been confirmed and the design will feature a TDP of less than 130W.
Although the new design will still be somewhat limited by the 1066MHz FSB that connects each six-core processor, this will certainly do some damage on AMD's hold of the multi processor systems, as each quad processor box will house 24 cores, each of higher performance than current Barcelona processors, clock-for-clock. AMD will only be left with the eight-way systems that reach 32 cores, when built with quad-core Opteron processors, and which are of limited availability.
Source: Dailytech
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